EDN

How to design an FPGA architecture tailored for efficiency and performance

Until relatively recently, the majority of FPGA architectures were developed using 4-input lookup tables (LUTs), where each LUT is constructed from SRAM bits storing digital (0 or 1) information. Also ...
TechRepublic

FPGA Based High-Speed A-OMS LUT & FIR System Design

A-OMS LUT design is an advanced approach for optimizing the size of a LUT required for the direct storage of complex computational values. It is known that in FPGAs the DSP blocks plays a major role ...
Semiconductor Engineering

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

A new technical paper titled “Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological University, Cornell University, ...
Electronic Design

Embedded FPGA Under the Hood

For the most part, embedded FPGA can be viewed as a “black box,” which is effectively as an RTL engine. However, sometimes it’s helpful to understand what’s going on underneath the hood to evaluate ...
EDN

Economical FPGA’s benefit from new downloadable design tool

Lattice Semiconductor Corporation announced the immediate availability of Version 4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite. The ispLEVER-Starter tools are a ...
Electronic Design

Redesigned FPGA Fabrics Solve Tough Mid-Range Challenges

Most FPGA vendors tend to focus on data-center workload applications, but a large percentage of users require different architectures for mainstream applications. Vertical markets needing mid-range ...
Semiconductor Engineering

Introduction To eFPGA Hardware

Intel builds processor chips and Arm provides processor cores to integrate into chips. Xilinx and Intel (nee Altera) build FPGAs and a range of new startups provide embedded FPGA (eFPGA) to integrate ...