Qualcomm is in talks to buy RISC-V-based AI accelerator and CPU developer Tenstorrent for $8 billion - $10 billion.
Synergy Quantum today announced a portfolio of quantum-safe silicon IP cores for RISC-V-based system-on-chip designs, ...
The newly minted chipmaking startup AheadComputing Inc. said today it has raised $21.5 million in seed funding to develop and commercialize a new artificial intelligence chipset based on the ...
The ability to effectively combine compute, AI, and graphics will become a key differentiator for platform competitiveness.
Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Synopsys announced its plans for expanding its processor intellectual ...
NextSilicon, a leader in next-generation computing solutions for AI and high-performance computing (HPC), today announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, ...
TOKYO--(BUSINESS WIRE)--Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on ...
From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan. In the Git ...
Use left and right arrow keys to seek audio. SiFive has just announced its new SiFive Performance P870-D, a new RISC-V processor with up to 256 cores, designed for data center applications. The new ...
When the number two provider of CPU designs jumps on the RISC-V train, it is a significant milestone. The open-source RISC-V design is on a roll, displacing Arm in many SoC development plans. ARC and ...
A new technical paper titled “Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection” was published by researchers at ETH Zurich. “Hardware fuzzing has recently gained momentum with many ...
The ARM926EJ-S™ processor features a Jazelle® technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces and memory management unit (MMU).